(a) Field of the Invention
The present invention relates to a semiconductor device having an alignment mark thereon and, more particularly, to a semiconductor device having an alignment mark for positioning the wafer during patterning circuit patterns in the semiconductor device.
(b) Description of Related Art
Reduction projection aligners have been widely used in manufacturing semiconductor devices. Methods of alignment used in a reduction projection aligners are roughly classified into two categories. A video image is utilized in methods of one category while diffracted light is utilized in methods of the other category. The present invention relates to the latter.
A conventional alignment method utilizing diffracted light is described in Proc. SPIE, Vol. 538, pp. 9-16 (1985) presented by Murakami et al. FIG. 1A is a schematic side view showing an optical system of the alignment apparatus as described in the document mentioned above while FIG. 1B is a plan view of an alignment mark shown in FIG. 1A. As shown in FIG. 1A, the alignment mark 11 is formed on a wafer 10, above which a reticle 12 is disposed. On one side of the reticle 12, a He--Ne laser unit 13 is disposed. The cross-section of a laser beam emitted from the laser unit 13 is transformed into a long elliptical profile by a lens system 14, then projected on the wafer 10 through a beam splitter 15, a mirror 16 and a projection lens 17.
The alignment mark 11 formed on the wafer 10 is comprised of square shaped unit markers 1 which are aligned in a single line at a pitch or period P. The wafer 10 is fixed to an unillustrated stage whose position is detected at any time. The alignment mark 11 is passed under the exposure of a laser beam 21 by moving the stage. Diffracted light is generated by the alignment mark 11 at that time and propagates in the opposite direction along the path of the laser beam to enter a spatial filter 18 after reflected by the beam splitter 15. After the zeroth order component of the diffracted light is removed by the spatial filter 18, the diffracted light enters a photo-sensor 19, wherein the diffracted light is converted into an electrical signal. The signal is then input into a signal processing unit 20 to be processed.
The position of the wafer 10 is detected relative to the stage in the moving direction of the stage through detecting the position where the alignment mark 11 passes under the laser beam 21. In a similar way, it is possible to form another alignment mark for detecting the position of the wafer 10 in a second direction perpendicular to the aforementioned direction. In this case, another alignment mark is formed perpendicularly to the above-described alignment mark, and the stage is moved in the second direction to allow the alignment mark to pass under the laser beam, whereby the position of the wafer in the second direction is detected.
Next, conventional patterns of the alignment mark will be described with reference to FIGS. 2A-2C. A pattern shown in FIG. 2A is one described by Murakami et al. and corresponds to the pattern shown in FIG. 1B. Although the actual number of unit marker 1 is seven, only five of them are illustrated in FIG. 2A to save space. In this example, unit marker 1 of 4 .mu.m.times.4 .mu.m in size (i.e. d.sub.1 =4 .mu.m and L=4 .mu.m in the drawing) are aligned in a single line so that the pitch P is 8 .mu.m. Here, each unit marker 1 is formed such that the length L of the unit marker in the direction in which the unit markers are aligned (hereinafter referred to as "column direction") becomes a half of the pitch P of the main diffraction grating to intensify the .+-.1st order components of the diffracted light as much as possible when the laser beam is projected.
FIG. 2B shows a second example of diffraction grating described in Proc. SPIE, Vol. 1088, pp. 238-247 (1989) reported by Magome et. al. In the first example, the length d.sub.1 of each unit marker in the direction of scanning a laser beam (referred to as a "scanning direction" hereafter) is equal to the length L in the column direction, i.e., 4 .mu.m whereas in the second example, unit marker 1 each of 2 .mu.m.times.4 .mu.m in size are disposed at a pitch P of 8 .mu.m. It is described by Magome et al. that a more accurate measurement can be obtained by reducing the length d.sub.2 in the scanning direction down to 2 .mu.m.
Nobutake et al. also shows a configuration in which a plurality of diffraction gratings (for example, seven) each having the layout shown in. FIG. 2A are disposed in the scanning direction as can be seen from FIG. 2C. When such a configuration is adopted, the positions of the diffraction gratings are all measured by successive laser scanning of the diffraction gratings, and the measured positions are averaged to obtain a more accurate position of the wafer.
Next, a description will be given for a conventional method for forming an alignment mark during a process in which interconnection patterns of a semiconductor device are also formed. Outline is such that contact holes are formed in an interlayer insulation film in an active element region. Subsequently, tungsten plugs are deposited in the contact holes followed by a step in which interconnection patterns are formed covering the tungsten plugs. During the pattern formation step, an alignment mark is formed outside the active element region simultaneously with the interconnection pattern formation on the tungsten plugs.
FIGS. 3A-3F show consecutive steps, as outlined above, for forming unit markers (4 .mu.m.times.4 .mu.m) of the alignment mark as viewed along line B--B' in FIG. 2A.
First, as shown in FIG. 3A, a photoresist 4 is coated to an interlayer insulation film 3 formed on a semiconductor substrate 2. Openings 21 are formed at locations where unit markers of an alignment mark are to be formed. At the same time, in an active element region, openings not shown in the drawing are formed in the photoresist 4 at locations where contact holes are to be formed. Subsequently, using the photoresist 4 as a mask, the interlayer insulation film 3 is etched by RIE (Reactive Ion Etching) using a mixed gas containing CF.sub.4 and CHF.sub.3 to form openings 22 constituting unit markers (FIG. 3B). At the same time, contact holes are formed in the active element region.
Next, as shown in FIG. 3C, a titanium nitride film 5 having a thickness of about 500 A (angstrom) is formed by sputtering, and a tungsten film 6 having a thickness of about 5000 A is formed over the entire surface by CVD. Subsequently, the whole surface is etched back in a mixed gas containing SF.sub.6 and N.sub.2. Since each opening 22 of the alignment mark has a relatively large area, the tungsten film 6 is completely removed from the central portion of each opening to leave the lower layer, i.e., the titanium nitride film 5 exposed although the tungsten film 16 remains on the sidewall of the opening. Then an aluminum alloy film 7 is deposited in a thickness of from 0.1 to 1 .mu.m by sputtering. Since the aluminum alloy film 7 does not have sufficient step-coverage characteristics, the aluminum alloy film 7 covers the openings asymmetrically, as shown in FIG. 3E. Moreover, the profile of the aluminum alloy film 7 covering each opening is irregular, varying from opening to opening.
Next, a photoresist is applied to the surface of the aluminum alloy film 7, then the semiconductor device is aligned using the alignment mark and followed by exposure and development steps. Subsequently, the aluminum alloy film 7 is etched by a mixed gas containing BCL.sub.3 and CL.sub.2 to form interconnection patterns. At that time, the aluminum alloy film 7 is also removed by etching from the area where the alignment mark exists, and a part of the titanium nitride film 5 on the sidewalls of the openings is also etched as shown in FIG. 3F.
In the above-described conventional alignment marks, each of unit markers constituting a diffraction grating has a relatively large area, for instance, 4.times.4 .mu.m or 4.times.2 .mu.m. Accordingly, when contact holes are filled with a metal layer such as tungsten film, the openings for the unit markers cannot be completely filled with the metal layer to leave un-buried portion thereof. If an aluminum alloy film is deposited on such openings during a process step forming interconnection patterns, the aluminum alloy film is asymmetrically formed on the openings as shown in FIG. 3E due to the pool step coverage of aluminum.
Moreover, since the aluminum alloy exhibits a different coverage profile at each unit markers, the regularity of reflected light to be used for alignment is deteriorated. In detail, when alignment is performed in a reduction projection aligner after the application of a photoresist, a He--Ne laser beam is irregularly reflected by the alignment mark. Accordingly, the spatial distribution of the diffracted light randomly varies so that the position of the stage deviates from the original position of the diffraction grating when the sensor attached to the aligner detects the diffracted light, thereby inducing an alignment error. In accordance with the proposal by Magome et al., the above-described problem can be somewhat mitigated by changing the size of each unit markers of a diffraction grating from 4.times.4 .mu.m to 4.times.2 .mu.m, as shown in FIG. 2B. However, a satisfactory result cannot be obtained.
In the case where the diffraction grating shown in FIG. 2A was used for alignment of a wafer, the alignment error was 0.7 .mu.m in term of 3.sigma. where .sigma. is a standard deviation of the alignment error. The results are shown in FIG. 5.
In the first conventional example shown in FIGS. 3A-3F in which a titanium nitride film is used as a barrier layer, a part of the titanium nitride film is removed when an aluminum alloy film is removed by etching. Accordingly, tungsten films remaining on the sidewalls of the openings peel off therefrom in a subsequent process and adhere again to an active element region so that circuit patterns are short-circuited thereby. As a result, the device yield rate decreases.
Another conventional example will be described in which a platinum silicide is used as a barrier layer. Similarly to FIGS. 3A-3F, FIGS. 4A-4D show consecutive steps for forming unit markers in the alignment marks as viewed along the line B--B' in FIG. 2A. In this example, openings 23 are formed in an interlayer insulation film 3 on a semiconductor substrate 2 similarly to the process steps shown in FIGS. 3A and 3B. A platinum film 8 is then formed over the entire surface by sputtering as shown in FIG. 4A. Subsequently, a heat treatment is performed at a temperature of some hundreds degrees centigrade to react platinum with silicon at the locations where the platinum film 8 directly contacts the silicon substrate 2, thereby forming a platinum silicide layer 9. The substrate 2 is then immersed into aqua regia to remove unreacted platinum (FIG. 4B).
Then a tungsten film 6 having a thickness of about 5000 A is formed over the entire surface by CVD as shown in FIG. 4C. Subsequently, the whole surface is etched back in a mixed gas containing SF.sub.6 and N.sub.2. Since the openings of the alignment mark have large areas, the platinum silicide film 9 is exposed to the outside at the central portion of the bottom surface of each opening, as shown in FIG. 4D.
Subsequently, an aluminum alloy film is formed similarly to the conventional example shown in FIGS. 3A-3F, and the patterning of aluminum alloy film is performed using the alignment mark formed as described above.
In the second conventional example shown in FIGS. 4A-4D where a platinum silicide film is used as a barrier layer, the platinum silicide film is exposed through the bottom surfaces of the openings of the alignment mark. Hence, it has a drawback that both an etch-back chamber for removing blanket tungsten and processing equipment used after the etch-back steps are contaminated by the exposed platinum silicide.